1. Field of the Invention
The present invention is generally in the field of semiconductor device fabrication. More specifically, the present invention is in the field of fabrication of compound semiconductor devices.
2. Background Art
It is generally desirable to merge the enhanced power handling capabilities of group III-V semiconductor power devices, such as III-nitride power transistors, and the energy efficiency and ease of fabrication of lower power silicon, or other group IV semiconductor devices, on a common die. However, traditional techniques for fabricating III-nitride power transistors make monolithic integration of those devices with commonly used silicon devices quite challenging.
For example, III-nitride power semiconductor device fabrication typically includes forming electrical contacts, such as ohmic source/drain contacts, having a low Specific Linear Contact Resistivity (SCLR). Conventional approaches to implementing electrical contacts displaying suitably low SCLR values on III-nitride devices have utilized aluminum as part of an electrode stack, and a noble metal, such as gold to form a capping layer of the stack. As a specific example, an electrical contact stack comprising pure films of titanium, aluminum, and nickel, capped with gold, has been widely used.
This conventional approach entails several significant drawbacks, however. One drawback is that use of gold as a capping layer is costly. Another is that gold has been found to diffuse through the electrode stack, as well as capping it, so that some gold undesirably appears at the interface of the electrical contact and the III-nitride semiconductor body. Yet another significant drawback to the use of gold as a capping layer is its propensity to contaminate a silicon fabrication process flow. Consequently, despite its favorable contribution to desirable SCLR values, the conventional approach to using gold as a capping layer for electrical contacts formed on III-nitride power semiconductor devices makes it particularly difficult to integrate those devices with silicon devices.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing an electrical contact for use on a group III-V semiconductor device that renders integration of group III-V and group IV semiconductor devices more efficient and cost effective by posing a reduced contamination risk to silicon, or other group IV semiconductor fabrication process flows.